The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to an apparatus and method of making strained channel complementary metal oxide semiconductor (CMOS) transistors having epitaxial lattice-mismatched epitaxial extension and source and drain regions.
Both theoretical and empirical studies have demonstrated that carrier mobility in a transistor can be greatly increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. Stress is defined as force per unit area. Strain is a dimensionless quantity defined as the change in a particular dimension of an item: for example, the change in the item's length, versus the initial dimension of that item: for example, its original length, when a force is applied in the direction of that dimension of the item: for example, in the direction of the length of the item's length. Strain can be either tensile or compressive. In p-type field effect transistors, the application of a compressive longitudinal stress, i.e. in the direction of the length of the conduction channel, creates a strain in the conduction channel which is known to increase the drive current of a PFET. However, if that same stress is applied to the conduction channel of an NFET, its drive current decreases.
It has been proposed to increase the performance of an NFET and a PFET by applying a tensile longitudinal stress to the conduction channel of an NFET and applying a compressive longitudinal stress to the conduction channel of a PFET. Such proposals have focused on masked processes involving the masking of a PFET portion of the chip and altering the materials used in shallow trench isolation regions near the conduction channel of the PFET to apply a desired stress thereto. Separate steps would then be performed to mask the NFET portion of the chip and alter the materials used in shallow trench isolation regions near the conduction channels of the NFET to apply a desired stress thereto. Other proposals have involved masked processes centered on modulating intrinsic stresses present in spacer features.
Silicon germanium is a desirable lattice-mismatched semiconductor for use in forming strained silicon transistor channels. A strain is created when a second semiconductor is grown onto a single-crystal of a first semiconductor when the two semiconductors are lattice-mismatched to each other. Silicon and silicon germanium are lattice-mismatched to each other such that the growth of one of them onto the other produces a strain in each which can be either tensile or compressive.
Silicon germanium grows epitaxially on silicon having a crystal structure aligned with the silicon crystal structure. However, because silicon germanium normally has a larger crystal structure than silicon, the epitaxially grown silicon germanium becomes internally compressed.
In other proposals using strained silicon, a substrate includes a very thick layer of silicon germanium. Alternatively, the bulk substrate consists of single-crystal silicon germanium. In either case, the silicon germanium layer or substrate is known as a relaxed layer because the strain is released by dislocations which form within the silicon germanium layer. When a single-crystal silicon layer is grown epitaxially on a relaxed layer of single-crystal SiGe, a tensile strain is produced in the epitaxially grown silicon crystal layer. This results in improved electron mobility, which improves the performance of an NFET.
However, such technique requires the SiGe to be relaxed, which requires that the SiGe layer be very thick, i.e. at least 0.5 to 1.0 μm thick. Improvements in the mobility of holes is difficult to obtain because to do so, the SiGe layer requires a large percentage of germanium, which can result in excessive dislocations in the SiGe crystal, causing yield problems. Further, processing costs can be prohibitive.
Other techniques such as graded Ge concentration and chemical mechanical polishing methods are used to improve the quality of the films. However, those techniques are plagued by high cost and high defect density.
Accordingly, it would be desirable to create a strain in the channel region of a PFET without the use of a thick SiGe crystal region. It would be desirable create a desired strain in a channel region of a device using an epitaxially grown SiGe film in source and drain regions of the PFET.
It would further be desirable for the SiGe film to be formed sufficiently thin to enable the SiGe film to apply a desirably high magnitude stress and avoid the SiGe film from becoming a relaxed film.
It would further be desirable to create a compressive strain to increase hole mobility in the channel region of a PFET by growing an epitaxial layer of SiGe in the source and drain regions of the PFET.
It would further be desirable to provide a process of forming raised source and drain regions extending above a level of the gate dielectric which include the lattice-mismatched semiconductor for creating a desirable strain in the channel region of the PFET.
It would further be desirable to provide a process for creating a desired strain in the channel region of a PFET without creating the same strain in the channel region of the NFET.
It would further be desirable to provide a structure and method for forming a lattice-mismatched semiconductor layer in source and drain regions of a PFET in close proximity to the channel region of the PFET while preventing the lattice-mismatched semiconductor layer from being formed in close proximity to the channel region of an NFET of the same integrated circuit.
It would further be desirable to provide a structure and method for forming a lattice-mismatched semiconductor layer in extension regions of a PFET in close proximity to the channel region of the PFET while preventing the lattice-mismatched semiconductor layer from being formed in extension regions in close proximity to the channel region of an NFET of the same integrated circuit.